1. Field of the Invention
The present invention relates to a logic simulator for carrying out simulation of a combinational circuit or sequential circuit.
2. Description of the Prior Art
A main object of logic simulation is to confirm a function of a logic circuit without actually realizing it with hardware. Particularly in case of LSI circuits, since the verification or alteration of the system becomes considerably difficult once it is constructed with hardware, this simulation method can be utilized as an effective means for verifying the correct operation of the circuit design. Moreover, because of a recent market trend of the verification time to be longer with increases in the circuit scale, a logic simulator applicable for processing a large-scale logic circuit at high speed is now expected.
As one of such logic simulation methods, there is a compiled method which is used mainly for verifying logic circuits used for computers.
In such a compiled method, logic circuits processed by simulation are respectively leveled in accordance with the order of signal propagation from the input stage to the output. Then, the operation of a logic element of each level is replaced with an instruction code of a computer, to obtain an output signal by executing these logic circuits in order of the respective levels.
Namely, as one of features of this compiled method, there can be mentioned high speed simulation realized by replacing each leveled logic element with an intrinsic instruction of a computer. However, because the above-mentioned leveling is applicable to processing only one-directional simulation, more improvement should be necessary for carrying out simulation of a circuit including loop elements such as flip-flops usually used in logic circuits. Moreover, in such a compiled method, since each logic circuit is replaced with a corresponding instruction of a computer to be subjected to the simulation, all of the process should be repeated again if any one of the logic circuits is changed to another in the middle of the design phase.
As another logic simulation method, there is an event-driven method.
This event-driven method means a method of carrying out simulation based on expressions of logic circuits including connection relation thereof given in a computer. Unlike the above-mentioned compiled method, the event-driven method does not require the leveling of logic elements, and is capable of simulation even in the presence of loops such as memory elements in each logic circuit. Moreover, since this method is so constructed as to estimate only a part (called an event hereinafter) to which is given a newly changed signal. Because of this a high speed simulation can be realized. Since the time required from input to output can be controlled by giving some appropriate delay time of each element to the element table, this simulation method can provide a state closer to an actual logic element.
In addition to the method of processing these two logic simulation methods by software of an ordinary computer, computers (or hardware processors) exclusively used for elevating the simulation speed are now developed.
Generally, both of the above-mentioned logic simulation methods are now widely used. However, it is also a fact that a greater enhancement of the processing ability (i.e., enlargement of the circuit scale and elevation of the processing speed) of the simulators is now required for logic systems or logic LSI's to be more largely constructed in response to the development of information industries. As a method of satisfying this requirement, a method of enhancing the logic simulation speed by using a suitable multiprocessor constructed with a plurality of computers is widely tried.
However, since the progress of computer or LSI technology can not catch up with the demand of enlarging the scale of logic systems and reducing the development time, it is very difficult to satisfy these conditions only by using the above-mentioned methods. Namely, in order to solve the situation, it should be necessary to provide a system which can be operated with ease by any one of ordinary logic system developers and realize a high speed simulation process.
The main reason why the present technology level can not answer the user's demand is that both of the above-mentioned simulation methods basically depend on a software process (this is essentially the same as the case where a special-purpose hardware processor is employed.) Namely, these methods are all established on the basis of the processing speed determined by repetition of the computer operation in which instructions are taken out and then executed one by one. Moreover, even if a multiprocessor arrangement is applied to these methods in order to process the instructions in parallel, in case of the compiled method, it becomes difficult to elevate the processing speed because of time delay of communication caused by collision of information between processors for transmitting an output signal. While in case of the event-driven method, it becomes difficult to obtain satisfactory processing ability because of conflict of access executed by all processors to the circuit table placed in a common memory. Such a multiprocessor method generally enlarges the device scale, therefore it becomes difficult to provide a small-scale system.
Namely, as far as these conventional methods are utilized in this type of simulation technology, it is very difficult to obtain a logic simulator having processing ability improved enough for answering the current demand of enlarging the scale of logic systems and reducing the development time.
Hereinafter, reference materials concerning the abovedescribed prior art are given.
1) Kozo Kinoshlta, Kunihiro Asada, Osamu Karatsu: Design of VLSI II, Iwanami Shoten, 1985, 191-210 (in Japanese). PA0 2) Kenji Omori, Akihiko Koike: Hardware Algorithm of The Logic Simulation Machine, Information Processing, Vol. 26, No. 6, 668-678, June 1985 (in Japanese). PA0 3) Tom Blank: Special-purpose Hardware Engine for Greatly Improving The Processing Speed in CAD, Nikkei Electronics, 1985, Apr. 8, 207-232 (in Japanese). PA0 4) Gregory F. Pfister: The Yorktown Simulation Engine, Proc. of DAC 19, 1982, 51-64. PA0 5) Akihiko Kolke, Kenji Omori, Toru Sasaki: Architecture of The Logic Simulation Machine, Information Processing Society, Vol. 25, No. 5, Sep. 1984. 864-872 (in Japanese). PA0 6) Hiroshi Yamada, Fumiyasu Hirose, Jun-ichi Niizuma, Tatsuya Shindo: Simulation Processor "SP", Electronic Information Communication Society, Vol.J71-D, No. 4, April 1988, 644-651 (in Japanese).
As described above, the conventional logic simulation method is essentially based on the software processing. Therefore, it is Impossible in principle to avoid such an essential condition that the instructions must be taken out and executed by a computer one by one. Accordingly, even if the processing speed of the computer can be elevated, it is still difficult to Improve the simulation speed when the scale of the circuit to be simulated is considerably large. Moreover, if a multiprocessor is applied to the compiled method in order to process the instructions in parallel, it becomes difficult to elevate the processing speed because of the time delay of communication for avoiding collision of information between processors when transmitting an output signal. In the case of the event-driven method, it also becomes difficult to enhance the processing speed because of conflict of access executed by all processors to circuit information placed on a common memory. Besides, such a multiprocessor method tends to enlarge the size of the logic simulator.
In short, the conventional logic simulator can not satisfy the recent demand of enlarging the logic circuit scale and reducing the development time of logic circuits.